module watchdog (rst_n,clk,feed,bark);
parameter watchtime = 100;

input clk,feed,rst_n;
output bark;

reg bark,feed_flag;
reg [10:0]cnt;

always@(posedge clk or negedge rst_n)begin
    if(!rst_n) begin
    feed_flag <=0;
    cnt<=0;   
    end
    else begin
    if(cnt == watchtime)begin
    cnt<=0;
    bark<=1;
    end
    else if(feed_flag == 1 && cnt != watchtime)begin
    cnt<=0;
    bark<=0; 
    end
    else begin
    cnt=cnt+1;
    end
    end

end

always@(feed)begin
     if(feed)
     feed_flag =1;
end

endmodule